Vertically-stacked gate-all-around polysilicon nanowire FETs with sub-lm gates patterned by nanostencil lithography
نویسندگان
چکیده
0167-9317/$ see front matter 2012 Elsevier B.V. A http://dx.doi.org/10.1016/j.mee.2012.07.048 ⇑ Corresponding author. E-mail address: [email protected] (D. Sacch We report on the top-down fabrication of vertically-stacked polysilicon nanowire (NW) gate-all-around (GAA) field-effect-transistors (FET) by means of Inductively Coupled Plasma (ICP) etching and nanostencil lithography. The nanostencil is used to form sub-lm GAA gates over polysilicon NW array channels with high aspect ratio, considerably simplifying the lithographic steps above regions with deep 3D topography and non-planar surface features. This process lead to fabrication yields larger than 70% and authors envisage even larger yields of P 85% with optimized mask design. Electrical measurements confirm the results obtained from similar devices fabricated with a standard lithography method while achieving higher density, larger reproducibility and yield, maintaining the performance improvement related with scaling. 2012 Elsevier B.V. All rights reserved.
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